Abstract

The System-in-Package (SiP) concept can be defined as of integrating several heterogonous components like semiconductor and passive devices into a single package or miniaturized module. This allows for extremely rapid and low cost development cycles.

This article will highlight the key benefits of having a SiP implementation especially for RF applications and how a company like Insight SiP can contribute to its customer success through Full-Turnkey Design Services while applying its own advanced packaging design methodology.

Introduction

The SiP approach to RF system integration has become essential to the miniaturization roadmap. Despite a long term tendency to integrate more and more functions within a single die (System-On-Chip concept) the never ending increase in complexity for small personal devices continues to drive the use of SiP to make complete systems. RF SiP can be realized using several types of technologies which are specific to each selected manufacturing supplier; therefore the SiP implementation will need to be tailored to the specific design rules based on different materials, physical dispositions and properties.

It is essential that the design house partner can combine its RF know-how with the unique ability to embed functions within the package irrespective of the packaging/assembly technology: organic substrates (BT, FR4…), multi-layer ceramic substrates (LTCC, HTCC, Thick film…), wire-bonding, flip-chip or thin film Integrated Passive Devices (IPD) on silicon or glass.

Two examples of SiP products developed by Insight SiP are shown below.

Figure 1 RF SiP Example

Figure 2 IoT Wearable SiP Example

The addition of ultra-miniature antennas to the RF SiP to create a so called “Antenna in Package” product (AiP) has been a fundamental part of the Advanced Technology Development. This technology has been successfully implemented in wireless products for Bluetooth Low Energy (BLE) and Ultra-Wide-Band (UWB) applications.

Why SiP approach addresses today’s challenge

With the massive adoption of consumer electronic products embedding more and more complex functions, it is important that new devices meet low power, smaller aspect-ratio requirements while remaining cost competitive. Therefore Engineers and Product Development Teams are facing the following challenges:

• Continued feature size shrinking is no longer reducing the cost per transistor starting from 65nm CMOS technology node
• SoC development time, NRE and risk of failure are increasing, to some extent, with every node (Gartner says it takes 9 times as much NRE for 7nm as it takes for a 28nm IC.)
• High growth markets (IoT, Automotive…) demand cost-effective integration of heterogeneous functions (Memory, MCU, GPU, Analogue, RF, MEMS, CIS …) in a small space.
• Lower power has replaced higher speed as the most important IC feature.
• Devices need to be wirelessly connected through existing RF protocols (eg cellular) or emerging networks (e.g. LPWAN like LoRa, SigFox, LTE-M, NB-IoT)

The SiP approach helps in meeting those paradigms because:

• The system partitioning offers More-than-Moore capabilities
• Their modularity simplifies adding heterogeneous functions to digital SoCs
• Combining multiple dies in one IC package will reduce power dissipation by 3 -10 X, versus mounting individually packaged dies onto a Printed Circuit Board
• Multi-die IC design and manufacturing flows are maturing, reducing NRE and development times making them economical also for low to medium volumes
• IDMs and fabless IC vendors have announced many interposer-based IC, are now ramping up production and have more such 2.5D-IC designs in progress.
• Major open foundries like TSMC have invested significantly into their own multi-die packaging line
• Most big OSAT companies have developed and offer WLP solutions
• Equipment and materials vendors have invested significantly and improved yield, throughput, quality and reliability to lower multi-die IC packaging cost
• Several EDA vendors offer user friendly modelling- and design tools to minimize development time and risk while reducing multi-die IC unit cost.

According to TechSearch International, 13.3 Billion SiPs were shipped in 2015. Almost 70% of the units were RF and connectivity modules like shown in the figure below.

Figure 3 2015 SiP Market by Device type (source Techsearch International)

Today’s high-performance semiconductor applications (Graphics, Computing, Networking) are primarily bandwidth and power limited. Samsung, IBM, Intel, HiSilicon, Nvidia and others have already demonstrated the benefits of combining several dies, stacked or side by side on an interposer. Compared to individual ICs on a PCB, very short die-to-die connections and very wide busses enable significant performance increases and, at the same time, power reductions.

Today’s fastest growing semiconductor opportunities (Mobile Devices, Automotive, and IoT Nodes) need a multitude of heterogeneous functions, to interact with the world around them. Combining multiple heterogeneous dies and sensors in a SiP meets their space, power and cost constraints.

The graph below shows how fast the communications market grows and how many heterogeneous functions these applications require, of course at low cost and low power dissipation.

Figure 4 Heterogeneous Function Market Share (source IC Insight)

Advanced Design Methodology for seamless integration

Insight SiP has a long track record of successful wireless module development including cell phone front end modules , Bluetooth modules and then a complete range of wireless/connectivity systems (GPS, Cellular 2G/3G/4G-LTE/5G, Bluetooth, WLAN, ISM RF, WHDI, BLE, UWB, NFC, RFID, 60GHz).

To address the rapid demand of RF and consumer SiP type products, Insight SiP has developed a proprietary advanced design methodology combining electromagnetic simulations (3D EM) together with circuit level simulation and optimization. Running exhaustive front-end EM simulation as an overall strategy before launching the first prototypes, allows reducing the number of iterations of engineering samples; this translates to cost savings to the end-customers and improved Time-to-Market.

This advanced design flow is summarized in the figures below.

Figure 5 Insight SiP Proprietary Design Methodology

The method uses a combination of circuit and electromagnetic simulation tools to create a design progressively from basic schematic representation to a complete 3D electromagnetic representation of the layout. Manufacturing is only carried out on a design for which the completed layout has been fully simulated; 2.5D or 3D electromagnetic simulations are used for the passive integration (laminate, LTCC, IPD) and harmonic balance or Spice modelling for the active circuits.

The complete design flow from initial schematic based circuit simulation to fully simulated and tested layout is shown in below.

Figure 6 Insight SiP Design Flow Schematic to tested Layout

An example of RF SiP using this proprietary methodology is shown below. It was developed in 6 months (from design to functional samples) for a smartphone application. It includes a GPS transceiver IC, a digital baseband IC and passive components (6mmx4mm, VFPGA package).

Figure 7 GPS SiP Example

For Antenna-in-Package (AiP) design, this design flow based on extensive 3D EM simulations allows designers to evaluate the best antenna performance in terms of radiation, gain, efficiency and range. This is key to optimize the effort during the RF tuning of the first engineering samples. Typical simulation outputs are shown below.

Figure 8 Antenna Performance Assessment by Simulation

Conclusion: Benefits of using Multi-die SiP and advanced packaging

All benefits described in this article of SiP or MCM are made in comparison to single die SoCs, mounted on a PCB which is the most widely used manufacturing procedure. In addition to recent cost reduction efforts for wafer and panel-level processing, the rapidly maturing eco-system for design and manufacturing of Multi-die ICs enables high value solutions.

In the identification of a SiP design house partner, industrialisation and production supports are key enablers. A company like Insight SiP has access to world leaders design rules for each SiP manufacturing technology and packaging. This allows selection of the most effective combination of process and production for each custom project.

It is essential, especially for complex RF systems, to have a close relationship with the different OSAT manufacturing partners, and Insight SiP has established a strong cooperation with major vendors like Amkor, AT&S, Tong-Hsing, Kyocera, SPIL… This is a key benefit during the industrialisation phase to secure production supply and yield improvement (e.g. RF/Antenna tuning during the ramp-up phase).

Author: Luc Engrand – New Product Business Development Manager – luc.engrand@insightsip.com

References:

Advanced Packaging Solutions for RF Systems, SAME 2012, Chakib El Hassan (Insight SiP) RF SiP Design For Portability, SAME 2008, Christopher Barratt (Insight SiP)

Multi-Die IC User Guide 2016.6, Electronic System Design Alliance